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| a FEATURES 128 Position Potentiometer Replacement 10 k , 50 k , 100 k , 1 M Power Shutdown: Less than 1 A 3-Wire SPI Compatible Serial Data Input +5 V to +30 V Single Supply Operation 5 V to 15 V Dual Supply Operation Midscale Preset APPLICATIONS Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Power Supply Adjustment GENERAL DESCRIPTION SDO 15 V Operation Digital Potentiometer AD7376* FUNCTIONAL BLOCK DIAGRAM AD7376 Q 7-BIT SERIAL REGISTER SDI CLK CS D CK 7 7-BIT LATCH R 7 VDD A W B SHDN VSS GND RS SHDN The AD7376 provides a single channel, 128-position digitallycontrolled variable resistor (VR) device. This device performs the same electronic adjustment function as a potentiometer or variable resistor. These products were optimized for instrument and test equipment applications where a combination of high voltage with a choice between bandwidth or power dissipation are available as a result of the wide selection of end-to-end terminal resistance values. The AD7376 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the SPI-compatible serial-input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. The variable resistor offers a completely programmable value of resistance between the A terminal and the wiper or the B terminal and the wiper. The fixed A to B terminal resistance of 10 k, 50 k, 100 k or 1 M has a nominal temperature coefficient of -300 ppm/C. The VR has its own VR latch which holds its programmed resistance value. The VR latch is updated from an internal serial-toparallel shift register which is loaded from a standard 3-wire serial-input digital interface. Seven data bits make up the data word clocked into the serial data input register (SDI). Only the last seven bits of the data word loaded are transferred into the 7-bit VR latch when the CS strobe is returned to logic high. A serial data output pin (SDO) at the opposite end of the serial register allows simple daisy-chaining in multiple VR applications without additional external decoding logic. The reset (RS) pin forces the wiper to the midscale position by loading 40H into the VR latch. The SHDN pin forces the resistor *Patent Number: 5495245 to an end-to-end open circuit condition on the A terminal and shorts the wiper to the B terminal, achieving a microwatt power shutdown state. When shutdown is returned to logic high, the previous latch settings put the wiper in the same resistance setting prior to shutdown as long as power to VDD is not removed. The digital interface is still active in shutdown so that code changes can be made that will produce a new wiper position when the device is taken out of shutdown. The AD7376 is available in both surface mount (SOL-16) and the 14-lead plastic DIP package. For ultracompact solutions selected models are available in the thin TSSOP package. All parts are guaranteed to operate over the extended industrial temperature range of -40C to +85C. For operation at lower supply voltages (+3 V to +5 V), see the AD8400/AD8402/ AD8403 products. SDI (DATA IN) 1 0 DX DX t DS t DH SDO (DATA OUT) 1 D'X 0 D'X t PD_MAX t CH 1 CLK 0 t CS1 t CL t CSS t CSH t CSW tS t CSH0 1 CS 0 VOUT VDD 0V 1 LSB ERROR BAND 1 LSB Figure 1. Detail Timing Diagram The last seven data bits clocked into the serial input register will be transferred to the VR 7-bit latch when CS returns to logic high. Extra data bits are ignored. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1997 AD7376-SPECIFICATIONS ELECTRICAL CHARACTERISTICS unless otherwise noted.) Parameter Symbol Conditions (VDD/VSS = 15 V 10% or 5V 10%, VA = +VDD, VB = VSS/0 V, -40 C < TA < +85 C Typ1 0.25 0.5 -300 120 200 7 -1 -1 -2 0 VSS Min -1 -1 -30 Max +1 +1 30 200 Units LSB LSB % ppm/C Bits LSB LSB ppm/C LSB LSB V pF pF A nA V V V V A pF V V mA mA mA mW %/% %/% kHz kHz kHz % s nVHz ns ns ns ns ns ns ns ns ns DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs) Resistor Differential NL2 R-DNL RWB, VA = NC Resistor Nonlinearity2 R-INL RWB, VA = NC Nominal Resistor Tolerance R TA = +25C Resistance Temperature Coefficient RAB/T VAB = VDD, Wiper = No Connect Wiper Resistance RW IW = 15 V/RNOMINAL Wiper Resistance RW IW = 5 V/RNOMINAL DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs) Resolution N Integral Nonlinearity3 INL Differential Nonlinearity3 DNL Voltage Divider Temperature Coefficient VW/T Code = 40H Full-Scale Error VWFSE Code = 7FH Zero-Scale Error VWZSE Code = 00H RESISTOR TERMINALS Voltage Range4 Capacitance5 A, B Capacitance5 W Shutdown Supply Current6 Shutdown Wiper Resistance Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Output Logic High Output Logic Low7 Input Current Input Capacitance5 POWER SUPPLIES Power Supply Range Power Supply Range Supply Current Supply Current Supply Current Power Dissipation8 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, 9, 10 Bandwidth -3 dB Bandwidth -3 dB Bandwidth -3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage VA, B, W CA, B CW IA_SD RW_SD ICM VIH VIL VOH VOL IIL CIL VDD/VSS VDD IDD IDD ISS PDISS PSS PSS BW_10K BW_50K BW_100K THDW tS eN_WB 0.5 0.1 5 -0.5 +0.5 +1 +1 +0 +1 VDD f = 1 MHz, Measured to GND, Code = 40H f = 1 MHz, Measured to GND, Code = 40H VA = VDD, VB = 0 V, SHDN = 0 VA = VDD, VB = 0 V, SHDN = 0, VDD = +15 V VA = VB = VW VDD = +5 V or +15 V VDD = +5 V or +15 V RL = 2.2 k to +5 V IOL = 1.6 mA, VLOGIC = +5 V, VDD = +15 V VIN = 0 V or +15 V 2.4 45 60 0.01 170 1 1 400 0.8 4.9 0.4 1 5 Dual Supply Range Single Supply Range, VSS = 0 VIH = +5 V or VIL = 0 V, VDD = +5 V VIH = +5 V or VIL = 0 V, VDD = +15 V VIH = +5 V or VIL = 0 V, VSS = -5 V or -15 V VIH = +5 V or VIL = 0 V, VDD = +15 V, VSS = -15 V VDD = +5 V 10%, or VSS = -5 V 10% VDD = +15 V 10% or VSS = -15 V 10% RAB = 10 k, Code = 40H RAB = 50 k, Code = 40H RAB = 100 k, Code = 40H VA = 1 V rms, VB = 0 V, f = 1 kHz VA = 10 V, VB = 0 V, 1 LSB Error Band RWB = 25 k, f = 1 kHz, RS = 0 4.5 4.5 16.5 28 0.0001 0.01 0.75 2 0.02 0.1 11 30 0.05 0.15 0.01 0.02 520 125 60 0.005 4 14 INTERFACE TIMING CHARACTERISTICS (Applies to All Parts [Notes 5, 11]) Input Clock Pulsewidth tCH, tCL Clock Level High or Low Data Setup Time tDS Data Hold Time tDH CLK to SDO Propagation Delay12 tPD RL = 2.2 k, CL < 20 pF CS Setup Time tCSS CS High Pulsewidth tCSW Reset Pulsewidth tRS CLK Rise to CS Rise Hold Time tCSH CS Rise to Clock Rise Setup tCS1 120 30 20 10 120 150 120 120 120 100 -2- REV. 0 AD7376 NOTES 11 Typicals represent average readings at +25C, VDD = +15 V, and V SS = -15 V. 12 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27. Test Circuit. 13 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 26. Test Circuit. 14 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 15 Guaranteed by design and not subject to production test. 16 Measured at the A terminal. A terminal is open circuit in shutdown mode. 17 IOL = 200 A for the 50 k version operating at V DD = +5 V. 18 PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 19 Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 10 All dynamic characteristics use V DD = +15 V and V SS = -15 V. 11 See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 1 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using both V DD = +5 V or +15 V. 12 Propagation delay depends on value of V DD, RL and CL see Applications section. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS (TA = +25C, unless otherwise noted) PIN CONFIGURATIONS PDIP & TSSOP-14 A1 B2 VSS 3 GND 4 CS 5 RS 6 CLK 7 14 W 13 NC A1 B2 VSS 3 GND 4 SOL-16 16 W 15 NC 14 VDD VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +30 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, -16.5 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +44 V VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD AX - BX, AX - WX, BX - WX . . . . . . . . . . . . . . . . . . . 20 mA Digital Input Voltages to GND . . . . . . . . . . 0 V, VDD + 0.3 V Digital Output Voltage to GND . . . . . . . . . . . . . . 0 V, +30 V Operating Temperature Range . . . . . . . . . . . -40C to +85C Maximum Junction Temperature (TJ MAX) . . . . . . . +150C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300C Package Power Dissipation . . . . . . . . . . . . (TJ MAX - TA)/JA Thermal Resistance JA P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92C/W SOIC (SOL-16) . . . . . . . . . . . . . . . . . . . . . . . . . . 120C/W TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C/W AD7376 TOP VIEW (Not to Scale) 12 VDD 11 SDO 10 SHDN 9 SDI 8 NC 13 SDO TOP VIEW CS 5 (Not to Scale) 12 SHDN RS 6 11 SDI 10 NC 9 NC AD7376 CLK 7 NC 8 NC = NO CONNECT NC = NO CONNECT ORDERING GUIDE Model k Temperature Range Package Description PDIP-14 SOL-16 TSSOP-14 PDIP-14 SOL-16 TSSOP-14 PDIP-14 SOL-16 TSSOP-14 PDIP-14 SOL-16 TSSOP-14 Package Options N-14 R-16 RU-14 N-14 R-16 RU-14 N-14 R-16 RU-14 N-14 R-16 RU-14 AD7376AN10 10 -40C to +85C AD7376AR10 10 -40C to +85C AD7376ARU10 10 -40C to +85C AD7376AN50 50 -40C to +85C AD7376AR50 50 -40C to +85C AD7376ARU50 50 -40C to +85C AD7376AN100 100 -40C to +85C AD7376AR100 100 -40C to +85C AD7376ARU100 100 -40C to +85C AD7376AN1M 1,000 -40C to +85C AD7376AR1M 1,000 -40C to +85C AD7376ARU1M 1,000 -40C to +85C Die Size: 101.6 mil x 127.6 mil, 2.58 mm x 3.24 mm Number Transistors: 840 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7376 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 -3- AD7376-Typical Performance Characteristics 100 PERCENT OF NOMINAL END-TO-END RESISTANCE - % RAB 0.5 0.4 0.3 0.25 0.20 TA = -55 C TA = +25 C R-DNL ERROR - LSB R-INL ERROR - LSB 75 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 TA = +85 C TA = +25 C 0.2 0.1 0 -0.1 -0.2 -0.3 TA = -55 C 50 TA = +85 C VDD = +15V VSS = -15V VA = 2.5V VB = 0V RAB = 50k 25 RWB 0 0 32 RWA 64 96 CODE - Decimal 128 -0.4 -0.5 0 16 32 VDD = +15V VSS = -15V RAB = 50k 0 16 32 48 64 80 96 CODE - Decimal 112 128 48 64 80 96 CODE - Decimal 112 128 -0.25 Figure 2. Wiper To End Terminal Percent Resistance vs. Code Figure 3. Resistance Step Position Nonlinearity Error vs. Code Figure 4. Relative Resistance Step Change from Ideal vs. Code 50 NOMINAL END-TO-END RESISTANCE - k 14 01H 10H 20H 40H 1.5 I w = 100 A, TA = +25 C DATA = 40H 1.2 49 R_INL - LSB 2 VDD = +15V VSS = -15V RAB = 50k NOMINAL VWA - V 12 10 8 6 4 48 0.9 47 46 2 CODE = 70H TA = +25 C VDD = +15V VSS = -15V RAB = 50k 7FH 0.6 0.3 45 -55 -35 -15 0 5 25 45 65 85 105 125 TEMPERATURE - C 0 0.25 0.5 0.75 1 1.25 1.5 1.75 IWA - mA 0 5 10 15 20 25 30 SUPPLY VOLTAGE (VDD - VSS) - Volts Figure 5. Nominal Resistance vs. Temperature Figure 6. Resistance Linearity vs. Conduction Current Figure 7. Resistance Nonlinearity Error vs. Supply Voltage 1.0 VA = 2.5V VB = 0V CODE = 40H RAB = 50k 20 15 WIPER CONTACT RESISTANCE - VWB/ T POTENTIOMETER MODE TEMPCO - ppm/ C 10 5 0 -5 -10 -15 -20 -25 VDD = +15V VSS = -15V VA = +2.5V VB = 0V -55 C < TA < +85 C RAB = 50k 16 32 48 64 80 96 CODE - Decimal 112 128 1000 900 800 700 600 500 400 300 200 100 0 -55 -35 -15 VDD = +5V VSS = -5V VDD = +15V VSS = -15V 5 25 45 65 85 TEMPERATURE - C 105 125 VDD = +5V VSS = 0V RAB = 50k 0.8 INL - LSB 0.6 0.4 0.2 0 5 10 15 20 25 30 SUPPLY VOLTAGE (VDD - VSS) - Volts -30 0 Figure 8. Potentiometer Divider Nonlinearity Error vs. Supply Voltage Figure 9. VWB/T Potentiometer Mode Tempco Figure 10. Wiper Contact Resistance vs. Temperature -4- REV. 0 AD7376 0.25 INL NONLINEARITY ERROR - LSB 0.25 40 0.20 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25 0 VDD = +15V VSS = -15V VA = +2.5V VB = 0V RAB = 50k 16 32 TA = +25 C TA = -55 C RHEOSTAT MODE TEMPCO - ppm/ C 0.20 0.15 0.10 35 30 25 20 15 10 5 0 -5 -10 0 16 32 VDD = +15V VSS = -15V RAB = 50k DNL - LSB 0.05 0 -0.05 -0.10 VDD = +15V VSS = -15V VA = +2.5V VB = 0V RAB = 50k 0 16 32 48 64 80 96 CODE - Decimal 112 128 TA = +85 C -0.15 -0.20 112 128 -0.25 48 64 80 96 CODE - Decimal 48 64 80 96 CODE - Decimal 112 128 Figure 11. Potentiometer Divider Nonlinearity Error vs. Code Figure 12. Potentiometer Divider Differential Nonlinearity Error vs. Code Figure 13. RWB/T Rheostat Mode Tempco 0 -6 -12 CODE = 7FH CODE = 40H CODE = 20H CODE = 10H RAB = 10k 0 -6 -12 GAIN - dB CODE = 7FH CODE = 40H CODE = 20H CODE = 10H CODE = 08H CODE = 04H CODE = 02H CODE = 01H A B W OP275 RAB = 1M 259.8 s VDD = +15V VSS = --15V GAIN - dB -18 -24 -30 -36 -42 -48 1k A B -18 -24 -30 -36 -42 CODE = 08H CODE = 04H CODE = 02H CODE = 01H CODE = 00H W OP275 VDD = +15V VSS = -15V VAMPL = 50mVrms CODE = 3FH VA = 2.5V VB = 0V f = 100 kHz 50m B Lw 40H 3FH -48 1M VDD = +15V VSS = -15V VAMPL = 50mVrms RAB = 1M HO5 s 5 S/DIV 100k 10k 100k FREQUENCY - Hz 100 1k 10k FREQUENCY - Hz Figure 14. 10 k Gain vs. Frequency vs. Code Figure 15. 1 M Gain vs. Frequency vs. Code Figure 16. Midscale Transition Glitch 0 -6 -12 GAIN - dB CODE = 7FH RAB = 50k CODE = 40H 20H 10H AMP = 50mV VDD = +15V VSS = -15V RL = 1M A B OP275 1.0 A2 12 CODE = 3FH VA = 12V VB = 0V f = 1 MHz VDD = +15V VSS = -15V THD - % 1.6 V DLY 128kHz 27.08 s 0.1 NON-INVERTING MODE TEST CKT FIG 36 0.010 -18 -24 -30 -36 -42 -48 08H 04H 02H 01H 0 VDD = +15V VSS = -15V VA = 10V p-p CODE = 40H RAB = 50k 5 0 5V 5V B Lw HO2 s -54 1k 2 S/DIV 0.001 0.0005 10 NON-INVERTING MODE TEST CKT FIG 35 100 1k 10k FREQUENCY - Hz 200k 10k 100k FREQUENCY - Hz 1M Figure 17. 50 k Gain vs. Frequency vs. Code Figure 18. Large Signal Settling Time Figure 19. Total Harmonic Distortion Plus Noise vs. Frequency REV. 0 -5- AD7376 0 -6 -12 20H 10H GAIN - dB CODE = 7FH 0 40H A2 2.9 V DLY 235.2 s -6 -12 -18 -24 -30 -36 01H A B W OP275 VDD = +15V VSS = -15V VAMPL = 50mVrms RAB = 100k VDD = +15V VSS = -15V GAIN - dB -18 -24 -30 -36 -42 -48 1k 10k VDD = +15V VSS = -15V VAMPL = 50mVrms CODE = 40H A W OP275 08H 04H 02H 50k 100k RAB = 1M 20m B Lw -42 -48 1M B HO2 s 10k 100k FREQUENCY - Hz -54 1k 100k 10k FREQUENCY - Hz 1M Figure 20. 100 k Gain vs. Frequency vs. Code Figure 21. -3 dB Bandwidth vs. Nominal Resistance Figure 22. Clock Feedthrough 0.1 0 -0.1 -0.2 GAIN - dB 90 RAB = 10k 50k 1M PSRR - dB 80 70 60 50 40 30 20 +PSRR VDD = +15V 10% VSS = -15V -PSRR VDD = +15V VSS = -15V 10% -PSRR VDD = +5V VSS = -5V 10% RON- 400 350 300 250 200 150 VDD = +15V VSS = -15V TA = +25 C VDD = +5V VSS = -5V -0.3 -0.4 -0.5 -0.6 -0.7 A 100k VDD = +15V VSS = -15V VAMPL = 50mVrms CODE = 40H -0.8 B W OP275 +PSRR VDD = +5V 10% VSS = -5V 10 100 1k 10k FREQUENCY - Hz 100k 100 50 0 -15 SEE FIGURE 38 TEST CIRCUIT -10 -5 0 5 VB - Volts 10 15 -0.9 10 10 100 10k 1k FREQUENCY - Hz 100k 1M Figure 23. Gain Flatness vs Frequency vs. Nominal Resistance RAB Figure 24. Power Supply Rejection vs. Frequency Figure 25. Incremental Wiper Contact Resistance vs. Common-Mode Voltage 10 IDD@VDD = +15V, VLOGIC = +5V 1.0 IDD@VDD = +15V, VLOGIC = 0V 4.0 SUPPLY CURRENT - mA SUPPLY CURRENT - mA SHUTDOWN CURRENT - 1.0 ISS@VSS = -15V, VLOGIC = +15V 0.1 VDD = +15V VSS = -15V 0.1 3.5 3.0 2.5 2.0 1.5 1.0 0.5 DATA = 3FH VDD = +15V, VSS = -15V VA = +2.5V VB = 0 TA = +25 C A DATA = 55H IDD@VDD = +5V, VLOGIC = +0.8V 0.010 0.010 IDD@VDD = +5V, VLOGIC = +5V RAB = 50k 0.001 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE - C 0.001 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE - C 0.0 1k 10k 100k 1M CLOCK FREQUENCY - Hz 10M Figure 26. Supply Current (IDD, ISS) vs. Temperature Figure 27. IA_SD Shutdown Current vs. Temperature Figure 28. IDD Supply Current vs. Input Clock Frequency -6- REV. 0 AD7376 3.5 3.0 INPUT LOGIC THRESHOLD VOLTAGE - Volts IMS 2.5 2.0 1.5 1.0 0.5 0 5 10 15 20 25 SUPPLY VOLTAGE (VDD) - Volts 30 VA = +5V VB = 0V VSS = 0V DUT V+ A W B VW IW = 1V/RNOMINAL VMS V+ VDD RW = VW2 - (VW1 + IW [RAW||RBW]) IW WHERE VW1 = VMS WHEN IW = 0 AND VW2 = VMS WHEN IW = 1/R Figure 33. Wiper Resistance Test Circuit VA VDD V+ B A W VMS V+ = VDD 10% OR VSS 10% Figure 29. Input Logic Threshold Voltage vs. VDD Supply Voltage PSRR (dB) = 20LOG PSS (%/%) = VMS% V+% ( VMS V+ ( 1600 1200 Figure 34. Power Supply Sensitivity Test Circuit (PSS, PSRR) IDD - A 800 VDD = +15V VSS = -15V A DUT B +18V 400 VDD = +5V VSS = 0V OR -5V 0 5 VLOGIC 10 15 W VIN OP275 -18V VOUT 0 Figure 30. Supply Current (IDD) vs. Logic Voltage Figure 35. Inverting Programmable Gain Test Circuit +18V PARAMETRIC TEST CIRCUITS DUT V+ B A W V+ = VDD 1LSB = V+/128 VMS A DUT B OP275 VIN W -18V VOUT Figure 31. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL) NO CONNECT Figure 36. Noninverting Programmable Gain Test Circuit A +18V W DUT A W B VMS IW VIN DUT B OP275 VOUT -18V Figure 32. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Figure 37. Gain vs. Frequency Test Circuit REV. 0 -7- AD7376 RSW = DUT B W ISW 0.1V ISW CODE = OOH PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation 0.1V VSS TO VDD Figure 38. Incremental ON Resistance Test Circuit NC VDD DUT VSS GND A W B ICM VCM NC Figure 39. Common-Mode Leakage Current Test Circuit The nominal resistance of the RDAC between terminals A and B are available with values of 10 k, 50 k, 100 k and 1 M. The final three characters of the part number determine the nominal resistance value, e.g., 10 k = 10; 50 k = 50; 100 k = 100; 1 M = 1M. The nominal resistance (RAB) of the VR has 128 contact points accessed by the wiper terminal, plus the B terminal contact. The 7-bit data word in the RDAC latch is decoded to select one of the 128 possible settings. The wiper's first connection starts at the B terminal for data 00H. This B-terminal connection has a wiper contact resistance of 120 . The second connection (10 k part) is the first tap point located at 198 (= RBA [nominal resistance]/128 + RW = 78 + 120 ) for data 01H. The third connection is the next tap point representing 156 + 120 = 276 for data 02H. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10041 . The wiper does not directly connect to the B terminal. See Figure 40 for a simplified diagram of the equivalent RDAC circuit. The general transfer equation that determines the digitally programmed output resistance between W and B is: RWB(D) = (D)/128 x RBA + RW (1) OPERATION The AD7376 provides a 128-position digitally-controlled variable resistor (VR) device. Changing the programmed VR settings is accomplished by clocking in a 7-bit serial data word into the SDI (Serial Data Input) pin, while CS is active low. When CS returns high the last seven bits are transferred into the RDAC latch setting the new wiper position. The exact timing requirements are shown in Figure 1. The AD7376 resets to a midscale by asserting the RS pin, simplifying initial conditions at power-up. Both parts have a power shutdown SHDN pin which places the RDAC in a zero power consumption state where terminal A is open circuited and the wiper W is connected to B, resulting in only leakage currents being consumed in the VR structure. In shutdown mode the VR latch settings are maintained so that, returning to operational mode from power shutdown, the VR settings return to their previous resistance values. A SHDN where D is the data contained in the 7-bit VR latch, and RBA is the nominal end-to-end resistance. For example, when VB = 0 V and A-terminal is open circuit, the following output resistance values will be set for the following VR latch codes (applies to the 10 k potentiometer). Table I. D (DEC) 127 64 1 0 RWB () 10041 5120 276 198 Output State Full-Scale Midscale (RS = 0 Condition) 1 LSB Zero-Scale (Wiper Contact Resistance) Note that in the zero-scale condition a finite wiper resistance of 120 is present. Care should be taken to limit the current flow between W and B in this state to a maximum value of 5 mA to avoid degradation or possible destruction of the internal switch contact. Like the mechanical potentiometer the RDAC replaces, it is totally symmetrical. The resistance between the wiper W and terminal A also produces a digitally controlled resistance RWA. When these terminals are used the B-terminal should be tied to the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general transfer equation for this operation is: RWA(D) = (128-D)/128 x RBA + RW (2) where D is the data contained in the 7-bit RDAC latch, and RBA is the nominal end-to-end resistance. For example, when VA = 0 V and B-terminal is tied to the wiper W the following output resistance values will be set for the following RDAC latch codes. RS D6 D5 D4 D3 D2 D1 D0 RS RS W RDAC LATCH & DECODER RS B R S = R NOMINAL /128 Figure 40. AD7376 Equivalent RDAC Circuit -8- REV. 0 AD7376 Table II. D (DEC) 127 64 1 0 RWA () 74 5035 9996 10035 Output State Full-Scale Midscale (RS = 0 Condition) 1 LSB Zero-Scale The typical distribution of RBA from device to device matching is process lot dependent having a 30% variation. The change in RBA with temperature has a -300 ppm/C temperature coefficient. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example connecting A-terminal to +5 V and B-terminal to ground produces an output voltage at the wiper which can be any value starting at zero volts up to 1 LSB less than +5 V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 128-position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to terminals AB is: VW (D) = D/128 x VAB + VB Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors, not the absolute value; therefore, the drift improves to 5 ppm/C. clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation they should be debounced by a flip-flop or other suitable means. When CS is taken active low the clock loads data into the serial register on each positive clock edge, see Table III. The last seven bits clocked into the serial register will be transferred to the 7-bit RDAC latch, see Figure 41. Extra data bits are ignored. The serial-data-output (SDO) pin contains an open drain n-channel FET. This output requires a pull-up resistor in order to transfer data to the next package's SDI pin. This allows for daisy chaining several RDACs from a single processor serial data line. Clock period needs to be increased when using a pull-up resistor to the SDI pin of the following device in the series. Capacitive loading at the daisy chain node SDO-SDI between devices must be accounted for to successfully transfer data. When daisy chaining is used, the CS should be kept low until all the bits of every package are clocked into their respective serial registers insuring that the data bits are in the proper decoding location. This would require 14 bits of data when two AD7376 RDACs are daisy chained. During shutdown (SHDN) the SDO output pin is forced to the off (logic high state) to disable power dissipation in the pull up resistor. See Figure 42 for equivalent SDO output circuit schematic. Table III. Input Logic Control Truth Table CLK L P CS L L RS H H SHDN Register Activity H H Enables SR, enables SDO pin. Shifts one bit in from the SDI pin. The seventh previously entered bit is shifted out of the SDO pin. Loads SR data into 7-bit RDAC latch. No Operation. Sets 7-bit RDAC latch to midscale, wiper centered, and SDO latch cleared. Latches 7-bit RDAC latch to 40H. Opens circuits resistor A-terminal, connects W to B, turns off SDO output transistor. AD7376 SDO Q 7-BIT SERIAL REGISTER SDI CLK CS D CK 7 7-BIT RDAC LATCH R 7 X VDD A W B SHDN VSS P H X H H L H H H X X X GND RS SHDN H H P H H L Figure 41. Block Diagram DIGITAL INTERFACING X The AD7376 contains a standard three-wire serial input control interface. The three inputs are clock (CLK), CS and serial data input (SDI). The positive-edge sensitive CLK input requires NOTE P = positive edge, X = don't care, SR = shift register. REV. 0 -9- AD7376 The data setup and data hold times in the specification table determine the data valid time requirements. The last seven bits of the data word entered into the serial register are held when CS returns high. At the same time CS goes high it transfers the 7-bit data to the VR latch. VDD 100 LOGIC Figure 43. Equivalent ESD Protection Circuit SHDN CS SDI SERIAL REGISTER D Q SDO A,B,W VDD CK RS CLK RS VSS Figure 44. Equivalent ESD Protection Analog Pins Figure 42. Detail SDO Output Schematic of the AD7376 All digital inputs are protected with a series input resistor and parallel Zener ESD structure shown in Figure 43. Applies to digital input pins CS, SDI, SDO, RS, SHDN, CLK -10- REV. 0 AD7376 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead Plastic DIP (N-14) 0.795 (20.19) 0.725 (18.42) 14 1 8 7 14-Lead TSSOP (RU-14) 0.201 (5.10) 0.193 (4.90) 0.177 (4.50) 0.169 (4.30) 0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN 14 8 PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 1 7 0.100 0.070 (1.77) (2.54) 0.045 (1.15) BSC SEATING PLANE 0.015 (0.381) 0.008 (0.204) PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 0.256 (6.50) 0.246 (6.25) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) SEATING PLANE 8 0 0.028 (0.70) 0.020 (0.50) 16-Lead Wide Body SOIC (R-16) 0.4133 (10.50) 0.3977 (10.00) 16 9 1 8 PIN 1 0.0118 (0.30) 0.0040 (0.10) 0.1043 (2.65) 0.0926 (2.35) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) 0.0291 (0.74) x 45 0.0098 (0.25) 0.0500 (1.27) BSC 8 0.0192 (0.49) SEATING 0.0125 (0.32) 0 0.0138 (0.35) PLANE 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) REV. 0 -11- -12- C3163-8-10/97 PRINTED IN U.S.A. |
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